1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to method of forming a capacitor electrode of a semiconductor memory device.
2. Description of the Related Art
Among semiconductor memory devices, a DRAM is known as being capable of arbitrarily outputting and inputting memory information. Since a memory cell in the DRAM having a structure composed of one transfer transistor and one capacitor is simple, it is widely used as most suitable one for higher integration of a semiconductor memory device.
For a capacitor of such a memory cell, a three-dimensional structure has been developed and used in accordance with further high integration of the semiconductor memory device. The reason why the capacitor has been formed into a three-dimensional structure is as follows. As semiconductor elements are made fine and are integrated in higher density, the contraction of an occupation area of a capacitor is inevitable. However, to secure a stable operation and reliability of the DRAM, it is necessary to secure a capacitance value larger than a certain value. For this purpose, the structure of an electrode of the capacitor is changed from a planar one to a three-dimensional one so that the surface area of the capacitor electrode is enlarged within the contracted occupation area.
There are a stack type capacitor and a trench type capacitor in the capacitors of three-dimensional structure of the memory cell of the DRAM. These structures have respectively merits and demerits. The stack type capacitor has high resistance against incidence of alpha rays or noises from circuits or the like, and stably operates even if the capacitance value is relatively small. Thus, it is considered that the stack type capacitor is effective even in a 1-gigabit DRAM in which a design standard of a semiconductor element is about 0.15 .mu.m.
As the stack type capacitor (hereinafter referred to as stacked capacitor), a fin-structured capacitor or a cylinder-structured capacitor has been vigorously studied and various improvements have been added (see Japanese Laid-Open (Kokai) Patent Publication Nos. Hei. 6-29463 and 4-264767). Recent proposals for such a stacked capacitor will be described below.
FIG. 4A to FIG. 4F are sectional views showing a process of forming a fin-structured capacitor, which is disclosed in Japanese Laid-Open (Kokai) Patent Publication No. Hei. 5-82750 (hereinafter referred to as a first prior art).
As shown in FIG. 4A, a field oxide film 102 is selectively formed on the surface of a silicon substrate 101. A gate electrode 104 is formed through a gate oxide film 103 at a portion to become one cell region on the silicon substrate 101. Further, a first N.sup.+ diffusion layer 105 connected to a bit line (not shown) and a second N.sup.+ diffusion layer 106 to become a storage node are formed in the silicon substrate 101 at both the sides of the gate electrode 104 so that a transfer transistor is structured. It should be noted that a gate electrode wiring 107 on the field oxide film 102 is connected to a gate electrode of an adjacent other cell (not shown).
Next, a silicon oxide film is deposited by a chemical vapor deposition method (hereinafter referred to as CVD method) so that an interlayer insulating film 108 is formed. Further, a silicon nitride film is deposited on the interlayer insulating film 108 so that an etching stopper film 109 is formed. Then, a first SiO.sub.2 spacer film 110 with a thickness of about 30 nm, a first N.sup.+ -type doped polysilicon film 111 with a thickness of about 20 nm, a second SiO.sub.2 spacer film 112 with a thickness of about 30 nm, a second N.sup.+ -type doped polysilicon film 113 with a thickness of about 20 nm, and a third SiO.sub.2 spacer film 114 with a thickness of about 30 nm are sequentially deposited.
As shown in FIG. 4B, the third SiO.sub.2 spacer film 114, the second N.sup.+ -type doped polysilicon film 113, the second SiO.sub.2 spacer film 112, the first N.sup.+ -type doped polysilicon film 111, the first SiO.sub.2 spacer film 110, the etching stopper film 109, and the interlayer insulating film 108 are sequentially dry etched by a reactive ion etching method (hereinafter referred to as RIE). Then, a contact hole 115 passing through these films is formed so that the second N.sup.+ diffusion layer 106 is exposed.
As shown in FIG. 4C, a third N.sup.+ -type doped polysilicon film 116 with a thickness of about 50 nm is formed on the inner surface of the contact hole 115 and on the third SiO.sub.2 spacer film 114.
As shown in FIG. 4D, the SiO.sub.2 spacer films 110, 112, and 114 and N.sup.+ -type doped polysilicon films 111, 113, and 116 laminated into a multilayer are finely processed by a photolithography technique and a dry etching technique to be patterned into a predetermined storage electrode shape 117.
As shown in FIG. 4E, the first, second and third SiO.sub.2 spacer films 110, 112, and 114 are removed by a wet etching technique using a hydrofluoric acid base chemical solution. Here, the etching stopper film 109 serves to protect the interlayer insulating film 108 so as not to be etched.
In this way, a first layer fin 118, a second layer fin 119, and a third layer fin 120 are formed, then the storage electrode 121 of three-layered fin structure is formed.
As shown in FIG. 4F, a capacitorinsulating film 122 is deposited on the surface of the storage electrode 121 of three-layered structure. Next, a fourth N.sup.+ -type doped polysilicon film is deposited and patterned by a dry etching process using the RIE so that a plate electrode 123 is formed. In this way, one transistor and one capacitor constituting a cell are formed.
A bit line (not shown) connected to the first N.sup.+ diffusion layer 105 is formed in a subsequent step.
As described above, in the first prior art, when the silicon oxide films (110, 112, 114) used for shaping an electrode are removed, the silicon nitride film 109 is used as the etching blocking layer so that the interlayer insulating film is not etched. The silicon nitride film can be used because the etching rate thereof by hydrofluoric acidis lower than that of the silicon oxide film.
However, when the silicon nitride film is used as the etching blocking layer for the interlayer insulating film, such a problem occurs that cracks or voids are generated in the interlayer insulating film because of a large stress of the nitride film, so that device characteristics are degraded. Also, there is such a problem that since hydrogen is hard to be diffused into the nitride film, even if a hydrogen annealing treatment is performed after fabrication of a device, hydrogen is not diffused into the transistor portion so that defects in the substrate are hard to be recovered.
In order to solve these problems, a method of forming a stacked capacitor without using a silicon nitride film is disclosed in Japanese Laid-Open (Kokai) Patent Publication No. Hei 6-196649 (hereinafter referred to as a second prior art).
According to the second prior art, a silicon oxide film into which impurities such as phosphorus are introduced, is used as a film for shaping an electrode, a silicon oxide film including no impurities is used as the upper portion of an interlayer insulating film, and the oxide film for shaping the electrode is removed by a vapor phase HF etching treatment. This method uses the fact that in the vapor phase HF etching treatment process, an etching rate of the silicon oxide film including impurities such as phosphorus is extremely larger than that of the silicon oxide film including no impurities.
However, in the second prior art, the specific etching process of the vapor phase HF treatment is required and a specific apparatus therefor is also required. Further, the direction and the like of the HF gas flow must be strictly controlled, so that the cost is also increased.